Senior DFT Architect - Multi-Chip SoC
Listed on 2026-11-04
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Engineering
Test Engineer, Hardware Engineer, Electronics Engineer
Eridu, a Silicon Valley hardware startup, seeks an experienced engineer to define the DFT architecture for a multi-chip SOC, covering test design, SDC constraints, and ATPG. You will work with RTL and gate-level simulations and oversee high-coverage scan techniques, including LBIST and streaming.
Expertise with Mentor/Synopsys test tools is preferred. Based in Saratoga, CA, the role offers a base salary in the range of 195,000–250,000 USD per year, with compensation determined by skills and
We are currently recruiting a Senior DFT Architect - Multi-Chip SoC for our team in Saratoga, CA, United States.
The position is based in Saratoga, CA, United States.
This opportunity is part of our work in Engineering.
The advertised compensation is 195..
We aim to respond to suitable candidates as soon as possible.
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