Senior RTL Networking Architect: Packet Buffering & QoS

A Silicon Valley hardware startup is seeking an experienced RTL Packet Buffering expert to help define and implement innovative Networking IC solutions. This role involves designing and optimizing high-speed networking chips while ensuring compliance with industry standards. Candidates should have 8-15 years of experience, proficiency in System Verilog and Verilog, and strong analytical skills. Join a pioneering team to shape the future of AI networking solutions, providing impactful contributions in a dynamic work environment.
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