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Senior RTL PCIe Architect; Gen
Job in
Saratoga, Santa Clara County, California, 95071, USA
Listed on 2025-12-15
Listing for:
Eridu Corporation
Full Time
position Listed on 2025-12-15
Job specializations:
-
IT/Tech
Systems Engineer, Hardware Engineer
Job Description & How to Apply Below
A Silicon Valley hardware startup is looking for a technical leader in PCIe microarchitecture with over 15 years of ASIC/SoC RTL design experience. You will develop high-performance buffering and protocol engines while owning RTL development. The role offers competitive compensation between $210,000 and $275,000 annually. Join a world-class team that is shaping the future of AI infrastructure and maximizing data center efficiency.
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Position Requirements
10+ Years
work experience
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