Senior SerDes Software Engineer — 224G PAM4 & PCIe
Listed on 2026-10-07
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Software Development
Senior Developer
Eridu AI in Silicon Valley seeks a senior Ser Des software engineer to lead development, bring-up, validation, and optimization of 224 Gb/s-per-lane interfaces. You will work on Ethernet Ser Des, PCIe, and UCIe in advanced silicon with cross-functional teams.
This senior role requires deep knowledge of Ser Des architecture, PHY init, link training, equalization, calibration, and system SI. Collaboration with analog, ASIC, firmware, and validation engineers is essential.
The following opening is for a Senior Ser Des Software Engineer — 224G PAM4 & PCIe Bring‑Up with Eridu AI.
We are currently recruiting a Senior Ser Des Software Engineer — 224G PAM4 & PCIe Bring‑Up for our team in Saratoga, CA, United States.
This is a strong role to take on the Senior Ser Des Software Engineer — 224G PAM4 & PCIe Bring‑Up role at Eridu AI.
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