Design Verification Engineer; Einfochips

Position:

Design Verification Engineer (eInfochips)

Experience:

6+ Years

Location:

San Jose, CA

• At least 6+ years of experience in System Verilog HVL and C++/C
• At least 6+ years of experience in UVM
• Experience in complete verification cycle, including development of test plans, BFM/Driver/Monitor/Scoreboard component development, integration in test bench, stress/corner testing, failure debugging, gate‑level simulations, assertions, and coverage closure
• Proficient in SVTB/UVM and C++ testbench
• Understanding of DSP is a plus
• Experience with Subversion repository management and Bugzilla bug tracking is a plus
• Proficient in debugging and assertions coding
• Verification closure with team

• At least 6+ years of experience in System Verilog HVL and C++/C
• At least 6+ years of experience in UVM
• Proficiency in scripting languages such as Make/Perl/Python or any other script language
• Any protocol experience is acceptable
• Ability to ensure customer satisfaction
• Effective reporting to customer on daily or weekly progress

• Medical, Dental, Vision Insurance
• 401k with Matching Contributions
• Short‑Term/Long‑Term Disability Insurance
• Health Savings Account (HSA) / Health Reimbursement Account (HRA) options
• Paid Time Off
• Tuition Reimbursement
• Growth Opportunities
• And more!

Work Arrangement:
Fully On‑Site. Must be able to travel to an Arrow Client office location as requested by Arrow Client leadership.

Location:

San Jose, CA.

Arrow is an equal opportunity employer. All applicants will be considered for employment without attention to race, color, religion, gender, age, sexual orientation, gender identity, national origin, veteran, or disability status.