Principal Digital Design Engineer, Reader IC

Principal Digital Design Engineer, Reader IC

Apply to the Principal Digital Design Engineer, Reader IC role at Impinj

We are looking for a Principal Digital Design Engineer to own the microarchitecture definition and front‑end implementation of key subsystems for Impinj’s next‑generation reader ICs. In this position you will use your experience in SoC subsystem definition, IP block microarchitecture, digital design and design‑for‑tests to take Impinj’s next‑generation reader ICs from concept through to production.

• Lead / own the microarchitecture definition and subsystem development for key IP blocks of Impinj’s next‑generation RAIN RFID reader ICs—from concept through parameterized design implementation, silicon test, characterization, and high‑volume production
• Collaborate with Product Management and Systems Engineering to define innovative features and performance targets that extend Impinj’s leadership in the reader IC market
• Leverage your broad knowledge of state‑of‑the‑art SoC integration tools, flows and methodologies and work closely with the CAD team to significantly advance the Impinj reader IC design flows and environment and ensure A0 tape‑out production quality
• Be the SoC DFX expert working with the product test engineering team to ensure scan insertion is completed optimally, ATPG is run and fault‑coverage metrics are generated and reviewed prior to tape‑out
• Oversee product subsystem definition, design and implementation to ensure on‑time, high‑quality delivery of an industry‑leading RAIN RFID reader IC
• Coordinate across disciplines to define priorities, align workflows and remove execution barriers

• Bachelor’s degree in electrical or computer engineering, or equivalent practical experience
• 15+ years of experience defining and implementing SoC IP block micro‑architecture and complex features, delivering parameterized, modular, scalable subsystem implementations for seamless SoC integration
• A deep understanding of state‑of‑the‑art SoC design and integration flows and methodologies including design‑for‑low‑power and multi‑voltage domain (UPF), design‑for‑test (scan insertion, ATPG, fault grading), IP and SoC register‑map creation/integration (.XML), timing‑constraint generation, cross‑domain clocking and synthesis‑flow timing convergence
• Proven success leading and delivering multiple complex mixed‑signal IPs from concept to first‑time right tape‑out and production
• Strong knowledge of microcontroller and system bus architectures (ARM and AMBA) including understanding of performance metrics
• Expertise translating protocol, functional descriptions and feature requirements into micro‑architecture and RTL implementation
• Strong proficiency with Verilog/System Verilog for RTL development, modeling and verification
• Experience evaluating and integrating third‑party IP such as Ethernet, USB and DDR4/DDR5 controllers
• Demonstrated technical leadership with broad organizational impact
• Excellent written and verbal communication skills

The typical base pay range for this role across the US is $179,700 - $269,600
. Individual base pay depends on various factors such as complexity and responsibility of the role, job duties, requirements and relevant experience and skills. Both market wage data and the mid‑point of the pay range is reviewed and used as the starting point for all new hire offers. Offers are made within the base pay range applicable at the time.

At Impinj certain roles are eligible for additional rewards, including merit increases, annual bonus and stock. These awards are allocated based on individual performance. In addition, certain roles also have the opportunity to earn sales incentives based on revenue or utilization, depending on the terms of the plan and the employee’s role. US‑based employees have access to healthcare benefits, a 401(k) plan and company match among others.

This position has access to technologies or data subject to U.S. export control regulations. Under these laws, the release or transfer of export‑controlled items or information to individuals who are not classified as "U.S. persons" (as…