Hardware Security Engineer; Devices & Services Security

Hardware Security Engineer (Devices & Services Security)

AG Consulting Partners, Inc. provides the pay range. This role’s 12‑month engagement expects onsite presence five days per week in Seattle, WA, and candidates must be located within a 30‑mile commuting radius and authorized to work in the U.S. without visa sponsorship.

$/yr – $/yr

The ideal candidate brings deep domain expertise and is able to articulate decision rationale effectively, contributing to the development of technical and business solutions. As a recognized subject matter expert, the Hardware Security Engineer is frequently consulted on cross‑functional initiatives and operates independently with minimal oversight. This role earns trust and respect through consistent leadership, accountability, and strategic insight, while ensuring delivery excellence across the program lifecycle.

• Analyzing System‑on‑Chip (SoC) security architectures to validate secure boot chains, root‑of‑trust enforcement, anti‑rollback protections, and cryptographic controls at the silicon level.
• Validating hardware security requirements through hands‑on testing of physical devices, evaluation boards, and chip samples across development and production life cycles.
• Executing hardware security testing techniques, including fault injection attempts, debug interface probing (JTAG/BDM), and resistance validation against physical attacks.
• Reviewing schematics, board layouts, and hardware designs to ensure correct implementation of secure key storage, tamper mitigations, and debug access restrictions.
• Verifying manufacturing security processes by assessing secure provisioning flows, key injection procedures, and production lifecycle state transitions.
• Inspecting manufactured hardware samples to detect unauthorized component substitution, malicious modification, or deviations from approved security designs.
• Assessing cryptographic implementations (RSA, AES, HMAC, PQC) embedded in hardware and firmware to confirm secure key handling and isolation.
• Collaborating with silicon vendors, OEMs, and manufacturing partners to remediate security findings and validate corrective actions at the device and chip level.
• Identifying systemic hardware security risks by correlating lab results, manufacturing data, and field observations across large‑scale device deployments.
• Documenting security assessments, validation outcomes, and risk mitigation plans in technical reports and communicating findings to engineering and leadership stakeholders.

• You love turning ambiguous, cross‑functional ideas into clear roadmaps and driving them through to delivery across multiple work streams.
• You are energized by influencing without authority and building strong, trust‑based relationships with senior leaders, engineers, and business partners.
• You are comfortable diving into complex technical domains, asking sharp questions, and connecting the dots between infrastructure, applications, data, and operations.
• You instinctively think in metrics and outcomes, using data to guide decisions, manage risk, and measure program success.
• You thrive in a matrixed environment, calmly navigating competing priorities, resolving conflict, and keeping stakeholders aligned.
• You care deeply about operational excellence and service quality, and you design programs with the end customer and long‑term sustainability in mind.
• You enjoy working independently with high ownership, while actively fostering transparency, collaboration, and accountability across teams.

• 5+ years of experience in hardware security, embedded systems security, or similar.
• Bachelor’s degree in Electrical Engineering, Computer Engineering, Computer Science, or related technical field.
• Strong knowledge of secure boot implementations, cryptography (RSA, AES, HMAC, PQC), and hardware security architectures (e.g., ARM Trust Zone or Intel SGX).
• Experience with manufacturing security processes, including secret provisioning and secure production flows.
• Knowledge of debug interface security (JTAG, BDM), anti‑rollback mechanisms, and fault injection protection.
• Familiarity with circuit design,…