Senior Physical Design Engineer

Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity.

The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at  .

We are seeking a Senior Physical Design Engineer to join our high-performance design team working on next-generation transceiver IPs targeting the TSMC 5nm, 3nm technology node.

In this role, you will take ownership of physical implementation from RTL to GDSII, ensure timing and power closure for ultra-high-speed designs, and collaborate closely with cross-functional teams to resolve challenges unique to advanced nodes and multi-gigabit transceiver architectures.

• Perform full-chip and block-level physical implementation including floor planning, placement, clock tree synthesis (CTS), routing, and physical verification for high-speed designs in TSMC 3nm.
• Collaborate with RTL and STA teams to ensure clean handoffs and convergent timing, area, and power.
• Work on advanced physical design techniques to support multiple voltage/frequency domains, hierarchical design, and physical-aware synthesis.
• Handle advanced physical design topics:
• EM/IR analysis and power grid optimization
• Congestion analysis and mitigation
• Clock domain crossing and skew optimization
• RC extraction-aware placement and routing
• Integrate IPs and top-level blocks with attention to physical interfaces, constraints, and timing alignment.
• Participate in defining floorplan strategy and chip partitioning for multi-gigabit transceivers.
• Perform ECO implementation and support tapeout signoff activities.
• Ensure DRC/LVS/ANT/CELL/ERC clean database using industry-standard physical verification tools.
• Use industry-standard tools (e.g., ICC2, Innovus, Voltus, Red Hawk, Calibre) for implementation and signoff.
• Develop and maintain automation scripts (Tcl, Python, Perl) for physical design flows and regressions.

• Bachelor’s or Master’s degree in Electrical Engineering, Electronics Engineering, or related field.
• 4+ years of experience in physical design with advanced technology nodes (preferably ≤ 5nm).
• Strong experience with:
• Floor planning, placement, CTS, routing, and IR drop mitigation
• Signoff checks (DRC/LVS/ANT/ERC) and debugging
• Timing closure collaboration with STA team
• Hands-on experience with tools such as Synopsys ICC2, Cadence Innovus, Calibre, Voltus.
• Experience in integrating high-speed IPs (e.g., Ser Des, PHYs) into SoC or chiplet environments.
• Experience in high frequence data path, DSP designs.
• Solid scripting skills for automation and productivity enhancement.

We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.