Staff Engineer - SerDes Verification

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The role involves building UVM/System Verilog test benches, running simulations, debugging timing and protocol issues, and evaluating signal integrity, jitter, BER, and eye diagrams. Close collaboration with design and hardware teams ensures compliance with protocols such as UCIe, PCIe, and DDR, delivering reliable, high‑performance silicon.

As a Ser Des Verification Engineer, you will be responsible for the verification and validation of high-speed Ser Des interfaces, including testing signal integrity, performance, and protocol compliance. You will work closely with hardware and design teams to ensure that Ser Des designs meet the required specifications, operating parameters, and quality standards. You are a team player who has excellent communication skills and experience collaborating with other engineers located in different sites/timezones.

You have strong analytical and problem‑solving skills and are willing to learn and ready to take on problems.

• Verification of Ser Des Designs:
  • Develop and execute verification plans and test benches for Ser Des IPs (Intellectual Property) and subsystems to ensure they meet functional and performance requirements.
  • Drive formal verification for the block and write formal properties and assertions to verify the design.
  • Estimate the time required to write the new feature tests and any required changes to the test environment.
  • Build the directed and random verification tests.
  • Review functional and code coverage metrics – modify or add tests or constrain random tests to meet the coverage requirements
• Testbench Development: Design and implement verification test benches using industry‑standard verification methodologies (e.g., UVM, System Verilog, VHDL).
• Simulation and Debugging:
  • Perform simulations, analyze results, and debug issues related to timing, protocol errors, and other design anomalies in Ser Des blocks.
  • Debug test failures to determine the root cause; work with RTL and firmware engineers to resolve design defects and correct any test issues
• Performance Evaluation: Evaluate and validate performance characteristics of Ser Des systems including jitter, bit error rates (BER), signal integrity, eye diagrams, and other key metrics.
• Protocol Compliance Testing: Verify adherence to relevant Ser Des protocols such as UCIe, PCIe, Ethernet, USB, DDR, Display Port, or custom protocols.
• Automated Testing: Develop automated regression tests to ensure the robustness and stability of the Ser Des design over multiple versions and iterations.
• Collaboration: Work closely with the design, hardware, and software teams to troubleshoot issues, implement fixes, and verify design changes.
• Documentation: Create detailed reports and documentation on verification results, test scenarios, and issues found during testing.
• Continuous Improvement: Provide feedback for design and verification process improvements and contribute to innovation in verification strategies and methodologies

• Experience in Ser Des verification or high-speed communication verification.
• Strong hands‑on experience with verification methodologies such as UVM, System Verilog, or other simulation‑based verification tools.
• Knowledge…