Research Scientist; Embedded & Quantum Security

About the Centre of Hardware Assurance (CHA)

The vision of Centre of Hardware Assurance (CHA) is to be the National Centre of Excellence for Hardware Assurance. The mission of CHA is to provide analysis capabilities from non‑invasive to invasive techniques in vulnerability assessment, forensics and certification of hardware devices and components. CHA comprises three main research groups: the Hardware Analysis team (HA), Circuit Analysis (CA) team, and Physical Analysis & Cryptographic Engineering (PACE) team.

The HA team focuses on developing new techniques using state‑of‑the‑art failure analysis tools for package and chip access, imaging and security assessment. The CA team researches the design and development of advanced algorithms and tools for automatic and efficient analysis of VLSI digital integrated circuits, utilizing deep learning techniques for better adaptability and productivity. The PACE team aims to advance side‑channel and fault analysis techniques for hardware security analysis.

Technological infrastructure and silicon chips are foundational to a nation’s economy and security. The proliferation of hardware IP and IoT—including vehicle networking, smart grids, and medical devices—has introduced complex security vulnerabilities. Integrated circuits, FPGAs, and non‑volatile memories face increasing threats from malicious actors. Ensuring the security of these systems is critical. Hardware security establishes trust and authenticity through secure design, access control, and communication.

This role addresses these challenges by securing embedded systems against classical attacks and emerging quantum threats. You will evaluate and implement security architectures, including future‑proof Post‑Quantum Cryptography (PQC) and Quantum Key Distribution (QKD), to ensure cryptographic agility within silicon.

• Evaluate state‑of‑the‑art embedded microcontrollers and working implementations of standardized cryptography algorithms, including the transition from classical to quantum‑resistant standards.
• Develop and test research methods for non‑invasive and semi‑invasive hardware security, with a specific focus on the integration of Post‑Quantum Cryptography (PQC) and Quantum Key Distribution (QKD) within embedded and IoT ecosystems.
• Design and execute experimental frameworks for device setup and testing, performing rigorous data analysis to assess the effectiveness of hybrid quantum‑security architectures.
• Provide technical evaluations and recommendations to internal and external project collaborators to enhance the security posture of next‑generation silicon and hardware IP.
• Manage project deliverables through the production of technical reports and documentation, ensuring compliance with international research standards and security frameworks.
• Lead the dissemination of research findings through high‑impact publications and presentations at top‑tier international academic conferences.
• Contribute to the long‑term project roadmap by identifying emerging threats in hardware forensics and developing mitigation strategies for future‑proofed silicon‑level trust.

• Minimally PhD or Masters in Electrical / Electronic / Computer Engineering with at least 6‑8 years of relevant research experiences or equivalent Prior experience in working with embedded systems is required.
• Prior experience with coding and evaluation of cryptography algorithms, specifically Post‑Quantum Cryptography (PQC) or Quantum Key Distribution (QKD), is required.
• Coding background in C, Java, Assembly, Python, or VHDL for analysis is required.
• Affinity for handling standard laboratory equipment such as oscilloscopes and microcontrollers.
• Good writing skills for writing proposals, reports and publications in good academic journals.
• Creative, curious, self‑motivated, and a team player with strong analytical and problem‑solving skills.

We regret that only shortlisted candidates will be notified.

Hiring Institution: NTU