Principal Design Team Leader

As the Principal Design Team Leader at Acceler Comm you will be working on 5G base stations on board satellites. This revolutionary technology is at the leading edge of non-terrestrial communications and will underpin the next generation of mobile standards giving complete coverage to the globe. Acceler Comm develop the baseband signal processing technology using hardware acceleration to generate world-leading error resilience capacity and power efficiency.

The Principal Design Team Leader will take a leading role in shaping the technical roadmap for extending the power efficiency for the latest generation space-qualified devices and then delivering this technology to our customers.

We are looking for a person with a proven track record of team leadership and delivering complex IP who has a real interest in all aspects of the Intellectual Property development life cycle.

This is a hands-on role requiring exceptional team leadership skills alongside technical skills to drive the design quality and delivery of Layer 1 IP. This role will play a pivotal part in the growth of Acceler Comm and our product portfolio

• Provide strategic vision to inform technical decision-making and planning at a company level working with colleagues from Algorithm System Architecture and Software teams.
• Take responsibility for the successful and timely delivery of projects by providing technical leadership
• Provide managerial leadership to build knowledge and support the team development
• Work closely with the exec team to translate product requirements into hardware team deliverables
• Support discussions with customers during presales and product development
• Oversee the implementation of designs targeting both FPGA and ASIC using industry standard techniques including the creation of UVM based test benches
• Lead Acceler Comms engineering methodology processes and design techniques integrating AI where possible.
• Nurture professional growth of team members through regular mentoring coaching and feedback

• Track record of building and leading high performing collaborative teams
• Expert knowledge of RTL design (Verilog System Verilog) for complex ASIC and FPGA products
• A strong skillset in delivery of digital designs for ASIC and FPGA
• Optimisation of timing and hardware resources for high throughput data or signal processing applications. Experience in power management techniques synthesis and timing analysis
• Expert user of EDA tools for simulation and synthesis
• Knowledge and appreciation of project management methodologies across the design lifecycle including agile and waterfall requirements capture and traceability.

• Knowledge of communications signal processing algorithms (such as error correction equalisation channel estimation beamforming)
• Understanding of UVM verification techniques or practical experience using UVM for IP verification
• Experience with high speed interfaces on and off chip such as AMBA PCI-E or JESD
• Understanding of using C/SystemC for design modelling and integration
• Experience in Technology Readiness Models
• Understanding of system architecture of a multi-disciplinary team project

We pay competitive salaries which depend on skills and experience.

We offer a bonus scheme which pays up to 20% of salary annually depending on performance. This is in addition to EMI share options issued periodically. We offer a range of good quality company benefits including pension and private health insurance.

Our offices on Southampton Science Park provide a great working environment with a coffee shop bike storage showers plenty of free parking and EV charging points.

We operate flexible working hours and offer hybrid working.

Required Experience:

Manager