Lead, -Speed ASIC Packaging & SI/PI Design
Listed on 2026-11-05
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Engineering
Packaging Engineer, Hardware Engineer, Electronics Engineer
Cisco Silicon One in California is seeking a Signal and Power Integrity Technical Lead to define, design, and verify ASIC packaging for high-performance platforms. You will develop design rules for ultra-high-speed signaling, assess SI/PI, and guide layout teams to optimize interposers, substrates, and PCBs.
You’ll lead architecture discussions, mentor junior engineers, and drive post-layout extraction and reporting to meet tight performance and reliability targets.
We would love to welcome a new Lead, High-Speed ASIC Packaging & SI/PI Design to our organisation in San Jose, CA, United States.
We are currently recruiting a Lead, High-Speed ASIC Packaging & SI/PI Design for our team in San Jose, CA, United States.
This is a strong opening to take on the Lead, High-Speed ASIC Packaging & SI/PI Design role at 020 Cisco Systems, Inc.
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