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Senior ASIC DV Engineer Speed Interconnects & HPC

Job in Sunnyvale, Santa Clara County, California, 94087, USA
Listing for: Avicena Inc.
Full Time position
Listed on 2025-12-16
Job specializations:
  • Engineering
    Systems Engineer, Electronics Engineer
Salary/Wage Range or Industry Benchmark: 150000 - 200000 USD Yearly USD 150000.00 200000.00 YEAR
Job Description & How to Apply Below
Position: Senior ASIC DV Engineer — High-Speed Interconnects & HPC
A pioneering technology firm in Sunnyvale, CA is seeking an ASIC Design Verification Engineer to ensure the functional correctness of high-speed low-power digital integrated circuits. The ideal candidate will have significant experience in ASIC verification, particularly using UVM and System Verilog. Responsibilities include developing test benches, defining verification plans, and debugging complex functional failures. This role is essential in driving innovation for cutting-edge silicon photonics solutions.
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Position Requirements
10+ Years work experience
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