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Design Verification Engineer
Job in
Sunnyvale, Santa Clara County, California, 94087, USA
Listed on 2025-12-19
Listing for:
Programmers.io
Full Time
position Listed on 2025-12-19
Job specializations:
-
Engineering
Systems Engineer, Test Engineer
Job Description & How to Apply Below
One of our leading client is looking for a Design Verification Engineer in Sunnyvale, CA.
Key Responsibilities:- Strong understanding of SV and UVM and good debugging skills.
- Understanding of AMBA protocols.
- Understand design specs and develop test plans based on functional and architectural requirements
- Build UVM/System Verilog-based verification environments for IP/subsystem/SoC level testing
- Develop directed and random testcases
, perform coverage analysis, and close functional/code coverage - Debug simulation failures and work closely with RTL designers to resolve issues
- Execute regression runs
, analyze results, and contribute to continuous improvements - Integrate and run power-aware simulations
, low power checks
, and work with UPF/CPF as needed - Collaborate with DFT/PD/RTL teams and post-silicon validation to ensure design quality across domains
- Document test environments, testplans, and results for internal and external reviews
Mid-Senior level
Employment typeFull-time
Job functionInformation Technology
IndustriesIT Services and IT Consulting
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