IC Layout designer

Avicena is a privately held company developing micro

LEDbased ultra-low power high bandwidth interconnects for chip-to-chip communications. This technology will revolutionize High-Performance (HPC) and Cloud computing, as well as other industries where low power interconnects are critical like camera sensors, autonomous vehicles, and aerospace.

Avicenais headquartered in Sunnyvale, California with a development center in Edinburgh, Scotland. The company was founded in 2019 by leading technologists from the optical networking industry witha track recordof delivering breakthrough products. ((Use the "Apply for this Job" box below). )

• Delivering the entire chip layout to the committed timeframe and within the required design requirements.
• Being responsible for theentire chip Tapeout and physical verification.
• Complete layout and verification of analogue and mixed-signal designs using industry-standard CAD tools.
• Be responsible for floor planning, custom layout and verifying against design rules.
• Work closely with design engineers to achieve optimal circuit performance and produce high-quality layout designs.
• Ability to solve layout design problems and provide innovative solutions.
• Contribute to complex IC development projects and prepare documents for knowledge sharing.
• Proven record of completing tasks on time or ahead of schedule while maintaining quality.

• Minimum of 10 years of relevant mask design/layout experience in mixed signal CMOS IC layout design at block & chip top level, including chip floor planning and integration.
• Must have experience in handling full chip layout and integration using state-of-the-art IC layout tools like Cadence Virtuoso.
• Must have experience with FINFET process.
• Must have adeep understanding of analogue circuit layout concepts in submicron CMOS technologies, device matching, shielding, etc.
• Experience with EM & IR Analysis and fixing for the layout closure.
• Experience in DRC, LVS, ERC, Antenna, and post layout extraction using Pegasus/Calibre verification tools.
• Knowledge of foundry command deck, PDK, fabrication & mask process.
• Must have design management techniques to ensure quality and deliver on schedule.