Senior ASIC Physical Design Engineer

About The Job

In this role, you’ll work to shape the future of AI/ML hardware acceleration. You’ll drive cutting‑edge TPU technology that powers Google’s most demanding AI/ML applications, contributing to custom silicon solutions and verifying complex digital designs focused on TPU architecture and AI/ML‑driven systems.

• Bachelor’s degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
• 7 years of experience in physical design (RTL to GDSII, floor planning, place & route, timing closure).
• Experience in Python, Tcl, or Perl scripting.

• Experience working with external partners on Physical Design closure.
• Experience in Static Timing Analysis with understanding of timing corners, margins and derates.
• Experience with Synopsys/Cadence PnR tools.
• Experience with backend flows (LEC, PI/SI, DRC/LVS, etc.).
• Understanding of DFT (Scan, MBIST, LBIST).
• Understanding of performance, power, and area trade‑offs.

• Participate in the Physical Design of complex blocks.
• Contribute to the design and closure of the full chip and individual blocks from RTL‑to‑GDS.
• Collaborate with internal logic and external teams to achieve the best Power/Performance Analysis (PPA) and conduct feasibility studies for new microarchitectures, optimizing runs for finished RTL.

Google is proud to be an equal opportunity workplace and is an affirmative action employer. We are committed to equal employment opportunity regardless of race, color, ancestry, religion, sex, national origin, sexual orientation, age, citizenship, marital status, disability, gender identity or veteran status. We also consider qualified applicants regardless of criminal histories, consistent with legal requirements. If you have a disability or special need that requires accommodation, please let us know by completing our Accommodations for Applicants form.