Signal and Power Integrity Engineer, PhD, University Graduate
Listed on 2025-12-25
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Engineering
Electrical Engineering, Systems Engineer, Electronics Engineer, Hardware Engineer
Signal and Power Integrity Engineer, PhD, University Graduate
Join to apply for the Signal and Power Integrity Engineer, PhD, University Graduate role at Google
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- PhD degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience.
- Experience with Signal and Power Integrity (SI/PI) fundamental concepts, microwave theory, or analog circuit design.
- Experience in AMS (Analog Mixed Signal) design.
- Experience in Matlab, Python, C++ to establish automation flows and data processing.
- Experience with SIPI or microwave modeling tool chains (e.g., HFSS, ADS, Sigrity, Siwave, etc.).
- Experience with Signal and Power Integrity (SI/PI) analysis and design for high-speed digital systems, including chip-package co-design concepts.
- Excellent programming and data analysis skills.
In this role, you’ll shape the future of AI/ML hardware acceleration and drive cutting‑edge TPU technology. You’ll work on custom silicon solutions powering Google’s TPU, contribute to innovation behind products loved by millions, and leverage design and verification expertise to verify complex digital designs focused on TPU architecture and AI/ML‑driven systems.
As a Signal Integrity/Power Integrity Engineer, you lead chip and package design, ensuring optimal SI and PI performance and system co‑design from concept to production. You collaborate within a cross‑functional team including chip design, intellectual property, system design, software, and vendors to drive signal and power design implementations on chip and advanced packages.
Responsibilities- Drive chip‑package‑system co‑design by performing SI/PI analysis and optimization, contributing to product definition and optimizing chip floorplan, power tree structure, net lists, etc., for HPC based on 2.5D/3D package technology.
- Collaborate with chip design team, system design teams, and suppliers to drive chip‑package SI/PI design goal, defining boundaries of chip design and exploring SI/PI and DFM trade‑off for package design closure for production.
- Provide feedback on chip floorplan considering package/system routability and SI/PI.
- Develop methodology to enhance accuracy and productivity.
- Support workflows for post‑silicon validation, qualification of high‑speed interface for NPI, high‑speed interface IP evaluation (serdes, memory), and high‑power, large DI/DT power integrity.
Google is proud to be an equal‑opportunity workplace and is an affirmative action employer. We are committed to equal employment opportunity regardless of race, color, ancestry, religion, sex, national origin, sexual orientation, age, citizenship, marital status, disability, gender identity or Veteran status. We also consider qualified applicants regardless of criminal histories, consistent with legal requirements. See also Google’s EEO Policy and EEO is the Law.
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