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Senior Manager of Semiconductor Technologies

Job in Sunnyvale, Santa Clara County, California, 94087, USA
Listing for: JRC Integrated Systems
Full Time position
Listed on 2025-12-27
Job specializations:
  • Engineering
    Systems Engineer, Electrical Engineering, Electronics Engineer
Salary/Wage Range or Industry Benchmark: 150000 - 200000 USD Yearly USD 150000.00 200000.00 YEAR
Job Description & How to Apply Below

Senior Manager of Semiconductor Technologies

Join to apply for the Senior Manager of Semiconductor Technologies role at JRC Integrated Systems
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About JRC

At JRC, we tackle some of the toughest challenges faced by the Department of Defense (DoD) and other government agencies. Our expertise in engineering innovation and semiconductor technologies allows us to deliver mission‑critical microelectronics solutions, aerospace systems engineering, and cutting‑edge research and development. By joining JRC, you’ll be part of a team that supports strategic deterrence and defense missions, playing a crucial role in ensuring the safety and security of the United States and its allies.

Shape

the Future of Microelectronics at JRC

Do you have a passion for cutting‑edge technology and driving the future of microelectronics? If so, we want to connect with you! We’re on the lookout for a dynamic Senior Manager of Semiconductor Technologies (Radiation‑Hardened Focus) to join our team, reporting directly to the Vice President of Semiconductor Technologies. In this high‑impact role, you’ll lead our Radiation‑Hardened Semiconductor Technology Division—a fast‑moving, strategic pillar of our innovation portfolio.

What

You’ll Do
  • Mentor, manage, and grow a small, high‑performing team of device physicists, circuit designers, and software engineers.
  • Contribute to defining the technical roadmap and strategy for the development of Radiation Hardened LEAP Standard Cell Libraries across multiple foundry technology nodes.
  • Serve as the technical authority on Semiconductor Device Physics for radiation effects, including Total Ionizing Dose (TID), Single Event Effects (SEE), and Single Event Upsets (SEU).
  • Direct the development, maintenance, and enhancement of in‑house software tools used for calculating and analyzing radiation‑induced error rates and circuit reliability.
  • Interface and collaborate directly with customers, and oversee project execution, timelines, resource allocation, technical quality control, and proactively address customer issues across execution and development efforts.
  • Oversee and execute simulations and advanced library characterization efforts to ensure cell resilience and optimize performance (PPA) in harsh environments. Drive continuous improvement in simulation accuracy, speed, and automation for library characterization flows.
  • Manage the relationship with external foundry partners to influence test chip execution efforts on Multi Product Wafer (MPW) runs.
  • Champion a culture of technical excellence, continuous learning, and rigorous scientific inquiry.
What You Bring to the Table
  • A Ph.D. in Electrical Engineering, Applied Physics, or a related field with 2+ years of direct industry experience, OR a master’s degree with 5+ years of direct industry experience, OR a bachelor’s degree with 7+ years of direct industry experience.
  • U.S. Citizenship is required due to the nature of defense‑related projects.
  • Deep foundational knowledge of semiconductor device physics and solid‑state materials.
  • Hands‑on experience with CMOS layout and design principles.
  • Extensive experience with semiconductor simulation tools, particularly for TCAD and/or library characterization (SPICE/Fast‑Spice).
  • Demonstrated experience working with commercial foundry technology nodes (e.g., FinFET, GAA, SOI, planar).
  • Proven ability to lead technical projects and drive results in a complex engineering environment.
Bonus Points
  • Direct experience in Radiation Hardened (Rad‑Hard) design methodologies, especially in mitigating Single Event Effects (SEE) and Single Event Upsets (SEU).
  • Direct experience in standard cell design, circuit design, layout and library characterization.
  • Proficiency in C++ coding and related scripting languages (e.g., Python, TCL) for tool development or advanced simulation/analysis automation.
  • 1+ years of experience leading a small team of engineers or serving as a technical team lead.
  • Strong desire and demonstrated capacity to quickly learn new physics, methodologies, and technology platforms.
  • Familiarity with standard cell design flows, including DRC/LVS, timing analysis, and power integrity.
Benefits
  • A competitive compensation package
  • An exceptional employee benefits program, providing support for our team members' well‑being and success
  • The chance to contribute to a high‑profile Department of Defense programs and make a positive impact
  • A collaborative work environment where teamwork, creativity, and innovation thrive
  • Opportunities for professional growth and development, helping you advance your career
Job Details
  • Seniority level:
    Director
  • Employment type:

    Full‑time
  • Job function:
    Engineering and Information Technology
  • Industry: Defense and Space Manufacturing
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Position Requirements
10+ Years work experience
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