DFT Engineer, Cloud

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• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience.
• 3 years of experience in DFT architecture, implementation, ATPG, and verification for SoCs.
• Experience with industry-standard test methodologies and platforms, such as (but not limited to) ATE, MBIST, JTAG, or System Level Test (SLT).

• Master's degree or PhD in Electrical Engineering, Computer Engineering, Computer Science, or a related field.
• Experience in DFT flow, including architecture, IP integration (Test controllers, TAP, MBIST), and interaction with synthesis and verification flows.
• Experience with industry-leading EDA tools for DFT, such as Synopsys (e.g., Design Compiler, DFT Max) or Siemens EDA (e.g., Tessent, Test Kompress).
• Experience with silicon process and technology nodes for high speed and low power consumption.
• Experience with various fault models (e.g., Stuck-at, Transition, Cell-Aware, Path Delay, etc.).

In this role, you’ll work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive cutting‑edge TPU (Tensor Processing Unit) technology that powers Google's most demanding AI/ML applications. You’ll be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's TPU. You'll contribute to the innovation behind products loved by millions worldwide, and leverage your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML-driven systems.

As a DFT Engineer, you will be responsible for defining, implementing and deploying advanced design‑for‑test (DFT) methodologies including Scan, MBIST, JTAG and iJTAG, for highly complex digital and/or mixed‑signal chips and/or IPs. You will define DFT architecture, and create DFT flows for complex next‑generation SoCs. In partnership with the Design and Physical Design teams, you will also be responsible for design verification of test logic, test pattern generation and debugging and test coverage issues.

• Complete all Test Design Rule Checks and Design changes to fix TDRC violations to achieve high test quality.
• Insert DFT logic, including scan chains, MBIST, TAP controller, Clock Control block, and other DFT IP blocks.
• Insert and hook up MBIST logic including test collar around memories, MBIST controllers, eFuse logic and connect to core and TAP interfaces.
• Design Verification of DFT logic and test pattern generation.
• Design and Implement System Level Test strategy.

Google is proud to be an equal opportunity workplace and is an affirmative action employer. We are committed to equal employment opportunity regardless of race, color, ancestry, religion, sex, national origin, sexual orientation, age, citizenship, marital status, disability, gender identity or Veteran status. We also consider qualified applicants regardless of criminal histories, consistent with legal requirements. See also Google's EEO Policy and EEO is the Law.

If you have a disability or special need that requires accommodation, please let us know by completing our Accommodations for Applicants form.