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Speed Analog EDA​/CAD Engineer

Job in Sunnyvale, Santa Clara County, California, 94087, USA
Listing for: LanceSoft
Part Time position
Listed on 2025-12-31
Job specializations:
  • Engineering
    Systems Engineer, Electronics Engineer
Salary/Wage Range or Industry Benchmark: 125000 - 150000 USD Yearly USD 125000.00 150000.00 YEAR
Job Description & How to Apply Below
Position: High-Speed Analog EDA/CAD Engineer

Candidate will be required to work onsite in office in Sunnyvale CA
Hybrid work schedule, in the office 3 days per week and for meetings as needed
Seeking an EDA/CAD Engineer to support SiGE and CMOS research & development and chip design located in Sunnyvale, CA.

Responsibilities
  • Install, customize and support external vendor PDK’s for both SiGe and CMOS processes
  • Install, customize and support Custom IC and RF CAD environment for the design of high-speed (10–40 Gb/s), broad-band, mixed-signal, integrated circuits for fiber-based wireline applications.
  • Lead and contribute to the development of design standards, IC development processes, CAD tools and design flows.
  • Execute and support layout efforts including archive and tapeout processes
Minimum Expertise Requirements
  • Expert in high-speed analog and mixed-signal IC design concepts and must demonstrate superior critical thinking skills, problem solving capabilities and engineering judgment.
  • Fluent with analog EDA front and back end tools
  • Cadence Virtuoso, ADE
  • Strong SKILL programming a must
  • Mentor Calibre (end user support and rule deck writing)
  • Detailed understanding of advanced high-speed analog & mixed-signal layout concepts
  • FlexLM license management
  • Strong UNIX/Linux knowledge
Minimum Experience Requirements
  • 5 years of experience working as a high-speed analog & mixed signal IC CAD professional is required
  • IC Technologies:
    High-speed IC technologies, including CMOS and bipolar.
  • IC Design Software:
  • Experience with configuring, documenting, and maintaining high speed analog IC design flows is a must.
  • Experience with transistor-level IC design and verification software, e.g. Cadence Composer, Cadence Virtuoso, Cadence Spectre, Virtuoso AMS, Mentor Calibre, Skill language, is a must.
  • General understanding of digital physical design flows, e.g. RTL coding, place and route, DRC/LVS verification.
  • Work Environment:
    Comfortable working in a fast-paced environment. Must be strong individual contributor, and also able to work as member of a small team. Must be able to support EPDA users and solve problems efficiently, effectively and rapidly.
Not required but preferred
  • Perforce
  • Ocean scripting and advanced modelling and simulation knowledge
  • Linux OS support
Education Requirements
  • BS 5 years
  • MS 4 years
  • PhD 3 years

Lance Soft

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