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Senior ASIC Design Engineer

Job in Sunnyvale, Santa Clara County, California, 94087, USA
Listing for: SQL Pager LLC
Full Time position
Listed on 2026-01-01
Job specializations:
  • Engineering
    Systems Engineer, Electronics Engineer
Job Description & How to Apply Below
Job Responsibilities

• To help develop an ASIC for our automotive and Data Center artificial intelligence computing architecture

• Participating in Architecture definition and modeling, verification test plan and testbench.

• Developing the micro-architecture specification, RTL in Verilog/System Verilog, performance/speed/power goals.

• Bring up the chip in lab, composing bring-up scripts.

• Collaborate with verification, software and system teams to ensure a successful product delivery.

Required Skills

• MS with 10+ years or PhD with 8+ years, 5+ years in ASIC design team lead.

• Experience in logic design on high-performance data center chip and integration of acquired IP blocks

• Good knowledge on ASIC design and verification methodologies and flows

• Hand-on experience:
System Verilog, C++, Perl/Python, UVM, Synthesis, Formal Verification, Static Timing Analysis

• Experience with processor design, AI/Deep Learning, PCIe/DDR, FPGA emulation

Proven track record as ASIC design on several production tape-outs

• Excellent written and verbal interpersonal skills
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Position Requirements
10+ Years work experience
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