Principal​/Senior​/CPU Design Engineer

Position: Principal/Senior Staff/Staff CPU Design Engineer
Principal/Senior Staff/Staff ASIC Design Engineer (RISC-V)

Client Overview

Client is building the first latency optimized SoC for their industry. Using its proven AI accelerator designs, Client is targeting best in class latency with order of magnitude improvements for years to come.

Low Latency has become the key enabler for the industry and other real-time application and the current industry’ state-of-the art is just not up to the task. Client has been developing its Neural Net Engines accelerators, optimizing it for Latency and achieving the best LPPA (Latency, Performance, Power, Area) in the field. We are now building the corresponding SoC, to deliver unrivaled products to mission-critical and real-time applications.

This is a fast-paced, intellectually challenging position, and you will work with a talented team driven by innovation and excellency. You’ll have relentlessly high standards for yourself and everyone you work with, and you’ll be constantly looking for ways to improve our products' performance, quality and cost.

We’re changing the meaning of low latency and we want individuals ready to rise up to the challenge and take the industry by storm.

Job Responsibilities

· We are seeking a dedicated CPU design engineer as part of ASIC for our mission using artificial intelligence computing architecture

· As CPU Design Engineer, you will be participating in Architecture definition and modeling, verification test plan and testbench architecture.

· You will be responsible for developing the micro-architecture specification, RTL in Verilog/System Verilog, performance/speed/power goals.

· Collaborate with Algorithm and Verification teams to design various functional IPs in RISC-V based complex SoC.

· Define a micro-architecture for the implementation and the usage of the functional block IP, possibly with external sourced IPs.

· Participate SoC level integration and verifications.

· Work with the Physical design team for the timing closure

Required Skills

10+years (Principal years (Senior Staff years (Staff) of general experience as a CPU Design Engineer for building complex SoCs.
◦ Experience in converting a module-level micro-architecture definition from given Marketing requirements.
◦ Expert in RTL Logic Design, CDC, RDC, Scan insertion, Lint, LEC., and synthesis with timing constraints.
◦ Experience in low-power design with UPF.
◦ Proficient in scripting with Tcl, Python and/or similar language.

At least gone through entire ASIC design phases from micro-architecture to post-silicon bringing-up and validation.

In-depth design knowledge in one or more of the following subjects:

• Instruction fetch and decode, branch prediction

• Instruction scheduling and register renaming

• Out-of-order execution

• Integer and Floating-point execution

• SIMD or Vector execution

• Load/Store execution, prefetching, memory ordering

• Virtualization, Hypervisor

• CPU Caches and Coherence,

• MMU, Memory/DRAM Controller, Latency-hiding

• Inter-connect bus fabric, AMBA, CHI, NoC

• Priority based Programmable Interrupt Controller

• Debug and Trace

• Low Power Implementation.

• Chip Security

• Cryptography

Nice to have
Experience in working with open-source design environments and tools.
Direct experience in RISC-V ISA specifications and the design compliances.
FPGA Design Prototyping for pre-silicon design validation
Experience in ISOASIL Requirements

Education
BSEE/BSCE or equivalent.
Master’s degree in science is preferred, but not required.

Featured benefits

• Medical insurance

• Vision insurance

• Dental insurance

• 401(k)

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