Physical Design Lead, Static Timing Analysis

Physical Design Lead, Static Timing Analysis

Share Physical Design Lead, Static Timing Analysis

Google Sunnyvale, CA, USA

X In most instances, this position requires in-person interviews as part of the hiring process.

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
• 10 years of experience in static timing analysis (STA), including 5 years of experience in a technical leadership capacity.
• Experience achieving full-chip timing convergence and authoring, reviewing, or validating timing constraints (e.g., Synopsys Design Constraints (SDC)).
• Experience using tool command language (Tcl) commands for timing analysis, timing closure, parasitic extraction, noise glitch, or crosstalk.
• Experience using electronic design automation (EDA) tools (e.g., Prime Time, Tempus, Timevision, or STAR-RC).
• Experience analyzing cross-chip clock distribution networks.

• Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture.
• 12 years of experience in the domain of static timing analysis and 5 years of experience in leading STA activities for SOC.
• Experience leading physical design or STA flow/methodology to successful tape-outs and shipping silicon.
• Experience analyzing data trends, semiconductor device physics, SPICE simulation, and full-chip static timing topics.
• Exceptional track record of on-time STA sign-off and delivery within physical design execution cycles.
• Drove full-chip timing convergence, timing constraint validation, and complex timing ECO implementation and sign-off.

In this role, you’ll work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive cutting-edge TPU (Tensor Processing Unit) technology that powers Google's most demanding AI/ML applications. You’ll be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's TPU. You'll contribute to the innovation behind products loved by millions worldwide, and leverage your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML-driven systems.

In this role, you will drive Static Timing Analysis (STA) in the physical implementation of Application-specific integrated circuits (ASIC) using advanced technology nodes. You will lead timing margin derivation, constraint development and validation, and timing closure of large, complex high performance compute ASICs. You will develop static timing methodologies, margins, automation scripts, and write documentation. Additionally, you will work with architecture, logic design, and Design for testing (DFT) teams to fully implement cross-functional design requirements.

The AI and Infrastructure team is redefining what’s possible. We empower Google customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity. Our customers include Googlers, Google Cloud customers, and billions of Google users worldwide.

We're the driving force behind Google's groundbreaking innovations, empowering the development of our cutting-edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Google Cloud, Google Global Networking, Data Center operations, systems research, and much more.

Individual pay is determined by factors…