Hardware Engineering Manager

Hardware Engineering Manager

Bolt Graphics Sunnyvale, California, United States

Bolt Graphics is a semiconductor startup based in Sunnyvale, CA building the fastest and most efficient graphics processors. We pride ourselves on our first principles approach to solving problems. We are energized by our mission to reduce the barrier of entry for content creation and consumption. Our goal is to enable everyone to easily create, simulate and consume immersive experiences as vividly as they can imagine them.

• Be Fearless: Unmute yourself. Test boundaries and get proven right.
• Remain Adaptable: Stay comfortable in a continuously changing world. If you’re wrong, concede and move on.
• Educate Your Ego: Selflessly collaborate towards our shared purpose.

We are looking for a highly technical, execution-oriented Hardware Engineering Manager to own the product lifecycle and system-level deployment of our disruptive
Zeus GPU platform
. Moving past legacy architectures, Bolt Graphics is redefining high-performance computing, advanced physics simulation (FP64), and real-time path tracing with a ground-up RISC-V controlled architecture thatoperatesas a standalone computing system.

In this role, you will bridge the gap between silicon architecture, system hardware design, and operations to deliver two critical form factors to market: high-density
PCIe Gen 5/6 accelerator cards
featuring innovative user-expandable memory (LPDDR5X + DDR5 SO-DIMMs) and ultra-scalable
2U HPC Server configurations
. You will lead the hardware product definition, manage tier-1 ODM/EMS delivery, and drive the hardware ecosystemrequiredto displace legacy, power-hungry GPU clusters.

Form
Factor Optimization:Own the PRD and hardware requirements for single/dual-chiplet PCIe accelerator form factors (e.g., Zeus 1c26/2c26) and multi-chip 2U rack-mount server architectures.

Memory Subsystem Strategy:Drive product requirements around our unique, high-capacity expandable memory subsystem, balancing the integration of on-board LPDDR5X with user-upgradable DDR5 SO-DIMM/DIMM slots to unlock up to 2.25TB per server node.

Native Network Integration:Define the roadmap for our integrated, high-bandwidth communication fabrics,utilizing native
400

GbE / 800

GbE interfaces
built directly into the accelerator toeliminatethe need for discrete NICs, loweringlatencyand TCO.

Standalone Subsystem Readiness:Collaborate with firmware and platform teams to ensure the embedded RISC-V control processor seamlessly runs standalone Linux subsystems, including server management features like integrated BMC and IPMI.

Thermal & Power Efficiency:Manage system trade-offs for highly efficient power targets (ranging from 120W single-slot boards up to 500W multi-chip server environments), ensuringoptimalbalance between air-cooled density and deployment in legacy data center infrastructures.

Silicon-to-System Execution:Drive cross-functional execution from recent chip tape-out through hardware validation, system-level NPI, and mass production.

Supply Chain & Partner Engagement:Partner with hardware engineering, board layout, signal integrity teams, and ODMs to source components,optimize

Bill of Materials (BOM) costs, and ensure manufacturing resilience for complex high-speed PCBs.

High-Speed Hardware Architecture:5+ years of experience defining or engineering high-performance PCIe-based add-in cards (AIC) or complex server systems. Deep understanding of
PCIe Gen 5.0 / 6.0electrical integrity, form factor constraints, and signal routing.

Memory & System Topology:Strong technical…