Senior RTL Design Architect AI ASICs
Listed on 2026-10-06
-
Engineering
Hardware Engineer -
Design & Architecture
Cerebras Systems, Sunnyvale, CA, is seeking a senior ASIC designer to drive RTL development, manage external vendors, and collaborate across verification, physical design and system teams. The role emphasizes front-end integration, high-speed interfaces, and silicon bring-up, with a hybrid work model in the Bay Area.
Ideal candidates have 8–15 years in complex RTL projects, strong networking and HPC/ML exposure, and a proven track record of successful silicon deliveries.
This posting is for the Senior RTL Design Architect for AI ASICs role at Anysilicon, based in Sunnyvale, CA, United States.
Our organisation is growing, and we are hiring a Senior RTL Design Architect for AI ASICs in Sunnyvale, CA, United States.
This opportunity is for the Senior RTL Design Architect for AI ASICs role at Anysilicon.
We are seeking a motivated Senior RTL Design Architect for AI ASICs to join Anysilicon in Sunnyvale, CA, United States.
(If this job is in fact in your jurisdiction, then you may be using a Proxy or VPN to access this site, and to progress further, you should change your connectivity to another mobile device or PC).