Design Verification Engineer

Job d:

Location:

Sunnyvale , CA;
Redmond , CA;
Austin , CASalary: USD 100-135 / Yearly (Full Time)

Employment Type:

Full Time Industry: Computer Software Client:
Wipro Contact:
Meghana Gorusu Company: SRI Tech Solutions

Job Title:

Design Verification Engineer Lcation:
Sunnyvale CA /Redmond WA/ Austin TX Onsite (Hybrid) Role
NO Remote Allowed

Key Responsibilities:

NO 18+ yrs profiles

No Contractors-IP level Verification
- SOC Design Verification
· Strong understanding of SV and UVM and good debugging skills.
· Understanding of AMBA protocols.
· Understand design specs and develop test plans based on functional and architectural requirements
· Build UVM/System Verilog-based verification environments for IP/subsystem/SoC level testing
· Develop directed and random testcases, perform coverage analysis, and close functional/code coverage
· Debug simulation failures and work closely with RTL designers to resolve issues
· Execute regression runs, analyze results, and contribute to continuous improvements
· Integrate and run power-aware simulations, low power checks, and work with UPF/CPF as needed
· Collaborate with DFT/PD/RTL teams and post-silicon validation to ensure design quality across domains
· Document test environments, test plans, and results for internal and external reviewsSRI Tech Solutions is an equal opportunity employer and does not discriminate on the basis of race, color, gender, religion, age, sexual orientation, national origin or citizenship status or ethnic origin, disability, marital status, veteran status, or any other occupationally irrelevant criteria.