TPU Interconnect & Packaging Engineer; .5D/3D
Listed on 2026-10-11
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Engineering
Systems Engineer, Packaging Engineer, Electronics Engineer
Google is seeking a Hardware Engineer in Sunnyvale to lead TPU interconnect and packaging efforts, defining architectural strategy for 2.5D/3D interposers, embedded bridges, and CPO modules as part of next-generation TPU systems.
You will collaborate across silicon photonics, substrates, and system integration, drive full-lifecycle qualification, and partner with OSATs to deliver high-bandwidth, energy-efficient interconnects for AI/ML workloads.
Are you ready to take on the TPU Interconnect & Packaging Engineer (2.5D/3D) role at Google LLC?
All applications are reviewed carefully by our team.
The position is based in Sunnyvale, CA, United States.
This opportunity is part of our work in Engineering.
The advertised compensation is 192..
We aim to respond to suitable candidates as soon as possible.
Full responsibilities and requirements are described in the listing above.
Learn more about the TPU Interconnect & Packaging Engineer (2.5D/3D) role in the description above.
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