ASIC Engineer, Design Test

Meta is building custom silicon to power the next generation of infrastructure and computing platforms. As an ASIC Engineer specializing in Design for Test (DFT) on the Infrastructure Silicon team, you will architect and implement testability solutions for complex, high-performance ASICs deployed at scale across Meta's data center infrastructure. In this role, you will define DFT strategies from RTL through silicon bring-up, ensuring manufacturability, diagnosability, and high fault coverage across large, multi-billion gate designs.

You will collaborate closely with design, physical implementation, and validation teams to deliver silicon that meets aggressive quality and time-to-market targets.

• Bachelor's degree in Computer Science, Computer Engineering, relevant technical field, or equivalent practical experience6+ years of experience in DFT engineering for complex ASIC or SoC designs, including scan insertion, ATPG pattern generation, and MBIST implementation
• Experience with industry-standard DFT EDA tools for scan compression, ATPG, and memory test (e.g., Tessent, Synopsys DFT Compiler, TetraMAX)
• Experience achieving high fault coverage targets across multiple fault models (stuck-at, transition delay, cell-aware) on multi-million gate designs
• Experience supporting silicon bring-up and manufacturing test, including ATE correlation and scan-based diagnosis
• Experience scripting in Tcl, Python, or Perl to develop and maintain DFT automation flows
• Familiarity with IEEE 1500, IEEE 1687 (IJTAG), or IEEE 1149.1 boundary scan standards and their application in infrastructure ASICs
• Background in post-silicon failure analysis and yield improvement using scan diagnosis and statistical defect modeling
• Experience with at-speed test methodologies including launch-on-capture and launch-on-shift for timing-critical paths
• Experience with DFT architecture for high-speed Ser Des interfaces, mixed-signal IP, or hierarchical test integration in large multi-die or chiplet designs