TPU RTL Design Engineer — AI/ML SoC Acceleration
Listed on 2026-10-18
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Engineering
Hardware Engineer, Test Engineer
Google is pursuing breakthroughs in AI/ML hardware acceleration. As a SoC Design Engineer, you’ll contribute to RTL design and verification for TPU architecture within data center accelerators, shaping how AI workloads are powered at scale.
You’ll collaborate across architecture, power, DV, and physical design teams to deliver robust chips and infrastructure. The role emphasizes cross-functional leadership, rigorous design practices, and interaction with software and system hardware
This posting is for the TPU RTL Design Engineer — AI/ML SoC Acceleration role at Google, based in Sunnyvale, CA, United States.
If your experience matches this role, we encourage you to apply.
All applications are reviewed carefully by our team.
The position is based in Sunnyvale, CA, United States.
This opportunity is part of our work in Engineering.
The advertised compensation is 138..
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