ASIC Design Engineer Intern

Meta is seeking an ASIC Design Engineer Intern to join our Infrastructure organization. Our servers and data centers are the foundation upon which our rapidly scaling infrastructure efficiently operates and upon which our innovative services are delivered. By holding this role, you will be an integral member of an ASIC team to build accelerators for some of our top workloads enabling our data centers to scale efficiently.

You will have an opportunity to participate in design and verification of advanced IPs using state of the art tools. Come work and learn alongside our expert ASIC engineers to build Green data center accelerators.

This is a 12 week internship.

• Currently has, or is in the process of obtaining, a Bachelor's degree in Electrical Engineering, Computer Engineering or related engineering fields
• Knowledge of Verilog or System Verilog or HLS
• Knowledge of Computer Architecture and Logic Design fundamentals
• Must obtain work authorization in country of employment at the time of hire, and maintain ongoing work authorization during employment
• Intent to return to full-time degree program after completion of the internship
• Currently has, or is in the process of obtaining, a Masters or PhD degree in Electrical Engineering, Computer Engineering or related engineering fields
• Experience with Lint, Synthesis, Formal or Physical Design tools
• Scripting capability with Python or Perl
• Experience with High Performance Computing
• Experience with Digital Signal Processing Techniques
• Creativity and problem solving capabilities