SOC Engineering, Architect

Category Engineering Hire Type Employee Job 19169 Base Salary Range $209000-$313000 Remote Eligible No Date Posted 10.07.2026 We Are

Synopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow.

You Are You have spent the better part of your career translating product ambition into silicon reality. You know that the hardest part of any SoC is not the individual IP blocks, it is making them work together as a coherent system that actually ships. You think in subsystems, not just components. You have sat in enough bring-up sessions to know that the decisions you make today about interconnect topology, power domains, or protocol alignment will either save or cost your team six months down the line.

You are comfortable walking into a room with conflicting requirements from software, verification, and implementation teams and walking out with an architecture that makes sense for all of them. You do not need perfect specs to start. You ask the right questions, model the critical paths, and make the call. You have a point of view on what makes a subsystem robust, and you are not afraid to push back when a proposal does not hold up under real-world constraints.

At Synopsys, you will work on IP subsystems that power everything from automotive AI to 5G infrastructure, and the architecture decisions you make will matter.

• Define subsystem architectures for memory controllers, interconnect clusters, compute blocks, power management units, or communication subsystems, translating product requirements into detailed specs that balance performance, power, area, security, and functionality
• Integrate multiple IP blocks into cohesive subsystems, ensuring proper interoperability, dataflow alignment, and interface compatibility with SoC-level interconnects and firmware requirements
• Lead architecture exploration activities including IP selection, subsystem modeling, and validation of candidate architectures using simulation and analysis tools
• Coordinate with SoC architects, verification teams, software engineers, and physical design groups to ensure subsystem feasibility, correctness, and alignment with platform constraints
• Define verification requirements for subsystem functionality, performance corner cases, power states, and protocol compatibility, working with DV teams to ensure comprehensive validation coverage
• Produce architecture documents, subsystem specifications, engineering guidelines, and implementation requirements that clearly communicate architectural intent to technical and non-technical stakeholders
• Participate in silicon bring-up, debug sessions, and subsystem-level performance characterization to validate architectural decisions in real hardware

• Bachelor's or Master's in Electrical Engineering, Computer Engineering, or related field with 15+ years of overall semiconductor experience
• 10+ years in semiconductor design, IP integration, or SoC/subsystem architecture roles with proven track record of delivering complex subsystems to production
• Deep expertise in Verilog and System Verilog for RTL design and simulation, with hands‑on experience using industry‑standard simulation tools
• Strong working knowledge of interface protocols such as AMBA APB, AXI, CHI, DDR, PCIe, Ethernet, USB, or UFS, including protocol‑level debugging and performance analysis
• Experience with synthesis, lint, CDC, low power design flows, and verification closure using…