Senior​/Principal Analog Mixed-Signal Design Engineer, Clocking

Avicena

Location:

Sunnyvale, CA, US

Job Title

Senior/Principal Analog Mixed-Signal Design Engineer, Clocking

About the Role

Avicena is developing high-speed parallel optical links built from arrays of microLED transmitters and photodetector receivers. We are looking for a clocking engineer to design and integrate the clock generation and distribution that keep many parallel lanes aligned. You will work on PLL integration, clock receivers, phase alignment and low-jitter distribution, from specification through silicon. We are hiring at senior through principal level;

title and scope will match experience.

Key Responsibilities

• Design and integrate clocking circuits: PLLs (licensed IP and custom blocks), clock receivers and buffers, phase interpolators or DLLs, duty-cycle correction and phase alignment.
• Design low-jitter clock distribution across many lanes.
• Analyze jitter and phase noise, and maintain the jitter budget with the clocking lead and system architect.
• Evaluate licensed PLL IP against requirements and support its integration.
• Analyze supply sensitivity and coupling, and work with layout on clock routing and shielding.
• Deliver behavioral models for system and verification use, and correlate them with transistor-level results.
• Support silicon bring-up and jitter measurement correlation.

At the principal level, you will also

• Set the technical direction for clocking architecture and the jitter budget with the clocking lead and system architect.
• Lead design reviews and define verification and signoff criteria for clocking blocks.
• Mentor engineers and review their designs.

Qualifications

Required

• MS in Electrical Engineering (or BS with equivalent experience) and 5+ years of clocking circuit design.
• Taped-out PLL, DLL, phase interpolator or CDR circuits.
• Jitter and phase-noise analysis with tools such as Spectre RF (PSS/pnoise).
• Design experience in FinFET or other advanced CMOS processes.
• Post-layout extraction and signoff experience.

Preferred

• Forwarded-clock or source-synchronous parallel interfaces.
• Clock distribution for multi-lane I/O.
• Integration of third-party PLL IP.
• Jitter modeling in MATLAB or Python.
• Lab jitter and phase-noise measurement.
• 10+ years with technical leadership of clocking designs through production (principal level).
• Analytical: reasons rigorously about jitter and noise.
• Ownership: drives clocking from budget to silicon.
• Collaboration:
  
  works across system, analog and layout teams.
• Clear communicator: explains budgets and trade-offs simply.

Key Competencies

• Analytical: reasons rigorously about jitter and noise.
• Ownership: drives clocking from budget to silicon.
• Collaboration:
  
  works across system, analog and layout teams.
• Clear communicator: explains budgets and trade-offs simply.