Silicon Packaging Engineer

Meta is looking for an experienced Silicon Packaging Engineer for its Ecosystem and Technical Operation team. The ideal candidate will be able to prioritize competing work streams across a cross-functional engineering environment based on impact, deadlines, and stakeholder needs. They will have experience with hardware development and integration of machine learning clusters, both server and fabric. They will be very familiar with AI/HPC hardware development, and will be data-driven and focused on the impact they can create as part of a engineering team.

The Meta Infrastructure team designs, builds, brings-up, tests and integrates hardware systems that power Meta's platforms, deployed in data centers worldwide, from silicon to sheet metal. Designs are published through the Open Compute Project Foundation. This is an opportunity to join our team and help us build some of the world’s most open and efficient machine learning platforms.

• Bachelor's degree in Computer Science, Computer Engineering, relevant technical field, or equivalent practical experience Master's degree in Materials Science, Mechanical Engineering, Electrical Engineering, or a related field, or equivalent practical experience
• 8+ years of experience in semiconductor packaging with direct ownership of advanced packaging development and assembly process and manufacturing
• In-depth knowledge of flip chip, 2.5D and 3D packaging technologies
• Experience taking products from concept to production, including development of manufacturing specifications, vendor qualifications, and improvement of manufacturing efficiencies and costs
• Experience communicating technical packaging decisions in writing and in reviews to cross-functional engineering and manufacturing stakeholders
• Experience working effectively with cross-functional teams
• Willingness to travel internationally, typically once per quarter
• Experience working with ODM, assembly packaging, OSAT, and foundry partners
• Knowledge of packaging and assembly industry standards
• Proven understanding of fanout advanced packaging technologies
• Hands-on experience in interposer or fanout package design for both organic and inorganic interposer with or without bridges such as CoWoS-L, CoWoS-R, EMIB, embedded fanout bridge from OSAT
• Proven technical understanding of the full range of semiconductor packaging design, SMT processes, PCB design and layout tools, failure mechanisms and analytical techniques
• In-depth knowledge of 2.5D and 3D packaging technologies, including silicon interposers, TSVs, and microbumps and advanced packages interaction with board-assembly constraints
• Master's degree or PhD in Materials Science, Mechanical Engineering, or a related discipline