ASIC Verification Engineer, Networking

ASIC Verification Engineer, Networking# ASIC Verification Engineer, Networking Sunnyvale, CA Hardware+ 4 more Apply nowMeta is hiring an ASIC Design Verification, Networking Engineer within the Infrastructure organization. We are looking for individuals with experience in Design Verification to build IP and System On Chip (SoC) for data center applications.

As a Design Verification Engineer, you will be part of a team working with experienced engineers across the industry, focused on developing ASIC solutions for Meta’s data center applications. You will be responsible for the verification closure of a design module or sub-system from test planning, UVM-based testbench development to verification closure. Along with traditional simulation, use other approaches like Formal and Emulation to achieve a bug-free design.

The role also provides ample opportunities to partner and collaborate with full stack software, hardware, ASIC Design, Emulation and Post-Silicon teams towards creating a first-pass silicon success.

---## ASIC Verification Engineer, Networking Responsibilities
* Define and implement IP/SoC verification plans, build verification test benches to enable IP/sub-system/SoC level verification
* Develop functional tests based on the verification test plan
* Drive Design Verification to closure based on defined verification metrics on test plan, functional and code coverage
* Debug, root-cause and resolve functional failures in the design, partnering with the Design team
* Collaborate with cross-functional teams like Design, Model, Emulation, and Silicon validation teams towards ensuring design quality meets defined verification and coverage goals
* Develop and drive continuous Design Verification improvements using the latest verification methodologies, tools, and technologies from the industry