ASIC Engineer, Implementation

Meta, 1180 Discovery Way, Sunnyvale, CA 94089

Job Description:

Meta's Silicon Engineering organization is seeking a Staff ASIC Implementation Engineer to lead the physical implementation and synthesis of complex custom ASICs. This role involves shaping architectural decisions and driving end-to-end implementation flows to deliver high-performance, power-efficient silicon solutions for Meta's AI and computing platforms.

Responsibilities:

• Lead end-to-end ASIC implementation flows, including logic synthesis, static timing analysis, and design-for-test integration.
• Define and own synthesis and implementation methodology, establishing reusable flows and constraints.
• Drive timing closure strategies across hierarchical design partitions, collaborating with RTL designers and physical design engineers.
• Develop and maintain synthesis scripts, constraint files, and automation infrastructure to enhance implementation quality.
• Generate SOC floor plans at various levels and enable block implementation owners to execute on synthesis and physical design.
• Perform top-level logical and physical connectivity analysis for timing and area optimization.
• Partner with architecture and RTL teams to provide feedback on design decisions impacting area, power, and timing.
• Define and enforce design rules and quality sign-off criteria for tape-out readiness.
• Identify and resolve cross-functional implementation risks, communicating status to stakeholders.
• Mentor engineers on implementation methodology and timing analysis techniques.
• Contribute to long-term silicon implementation strategy and evaluate new EDA tools and technologies.

Qualifications:

• Bachelor's degree in Computer Science, Computer Engineering, or a relevant technical field.
• 8 years of experience in ASIC implementation, including logic synthesis and timing closure for complex designs.
• Experience with EDA tools such as Synopsys Design Compiler, Fusion Compiler, or Cadence Genus.
• Experience managing synthesis constraints including SDC and UPF.
• Experience driving timing closure across multi-million gate designs with complex timing exceptions.

Skills:

• Expertise in ASIC implementation and synthesis methodologies.
• Strong knowledge of static timing analysis and design-for-test integration.
• Proficiency in scripting languages for automation.
• Ability to collaborate effectively with cross-functional teams.
• Strong problem-solving skills for timing closure and design optimization.