Physical Design Engineer; PnR

Avicena is developing high-speed parallel optical links built from arrays of microLED transmitters and photodetector receivers. We are looking for a physical design engineer to implement and close digital blocks and top-level partitions of our mixed-signal ASIC. You will work with the PnR lead to take designs from netlist to clean signoff.

Key Responsibilities

• Run synthesis, floor planning, placement, clock tree synthesis and routing for blocks and partitions.
• Close timing across modes and corners, and implement ECOs.
• Run signoff checks: STA, IR drop and EM, physical verification and logical equivalence.
• Integrate analog macros and repeated arrays following the macro handoff checklist.
• Maintain and improve implementation scripts.
• Support tapeout and post-tapeout ECOs.

Qualifications

Required

• BS or MS in Electrical or Computer Engineering with 3+ years of ASIC physical design.
• Hands-on experience with Cadence Innovus or Synopsys ICC2/Fusion Compiler, and STA with Tempus or Prime Time.
• Physical verification with Calibre or Pegasus.
• Tcl and Python scripting.
• FinFET implementation experience.

Preferred

• Mixed-signal top-level integration.
• IR/EM analysis and fixing.
• DFT-aware implementation, such as scan chain reordering.
• Hierarchical implementation.
• Detail-oriented: closes issues completely.
• Collaboration:
  
  works closely with the PnR lead and design teams.
• Ownership: delivers assigned blocks on schedule.

Key Competencies

• Detail-oriented: closes issues completely.
• Learner: picks up new flows quickly.
• Collaboration:
  
  works closely with the PnR lead and design teams.
• Ownership: delivers assigned blocks on schedule.

Location:

Sunnyvale, CA, US