Digital Architect

Avicena is developing high-speed parallel optical links built from arrays of microLED transmitters and photodetector receivers. We are looking for a Digital Architect to define the digital architecture of our link ASIC: the data path, link management, and the calibration and training engines that control the analog circuits. You will turn system requirements into clear specifications that the RTL, verification and firmware teams can build from.

• Define digital architecture and micro-architecture specifications for the data path, link management and control functions of a parallel optical link ASIC.
• Architect calibration, training and adaptation engines that set and track analog circuit parameters, and partition functions between hardware and firmware.
• Define analog/digital interfaces, timing and control loops with the system architect and the TX, RX and clocking leads.
• Define the register map and host control interface with the firmware team.
• Lead performance, latency, area and power trade-off studies.
• Develop architecture models in C/C++, Python or SystemC to validate algorithms and generate reference data for verification.
• Define clocking, reset and clock-domain-crossing architecture with the implementation team.
• Review RTL and verification plans for alignment with the architecture, and support DFT architecture.
• Support post-silicon bring-up of digital features.

• BS or MS in Electrical or Computer Engineering with 12+ years of digital ASIC design, including 5+ years defining architecture or micro-architecture for production chips.
• Deep experience with high-speed link digital design: framing, encoding and scrambling, error detection or FEC, lane deskew and alignment, and link training.
• Experience architecting digital control and calibration for analog/mixed-signal circuits.
• Strong System Verilog/Verilog background and understanding of synthesis, timing and power implications.
• Modeling experience in C/C++ or Python.
• Multi-clock design and CDC/RDC architecture.

• DSP and adaptation algorithms for communication links.
• Hardware/firmware co-design.
• Technical leadership of design teams.
• Systems thinker: connects requirements, algorithms and hardware cost.
• Clear writer: produces specifications others can implement without guessing.
• Collaboration:
  
  bridges analog, digital and firmware teams.
• Technical judgment: makes and defends trade-offs with data.

Avicena is developing high-speed parallel optical links built from arrays of microLED transmitters and photodetector receivers. We are looking for a Digital Architect to define the digital architecture of our link ASIC: the data path, link management, and the calibration and training engines that control the analog circuits. You will turn system requirements into clear specifications that the RTL, verification and firmware teams can build from.

• Define digital architecture and micro-architecture specifications for the data path, link management and control functions of a parallel optical link ASIC.
• Architect calibration, training and adaptation engines that set and track analog circuit parameters, and partition functions between hardware and firmware.
• Define analog/digital interfaces, timing and control loops with the system architect and the TX, RX and clocking leads.
• Define the register map and host control interface with the firmware team.
• Lead performance, latency, area and power trade-off studies.
• Develop architecture models in C/C++, Python or SystemC to validate algorithms and generate reference data for verification.
• Define clocking, reset and clock-domain-crossing architecture with the implementation team.
• Review RTL and verification plans for alignment with the architecture, and…