Senior Physical Design Engineer ASICs
Listed on 2026-11-04
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Engineering
Electronics Engineer, Hardware Engineer
Tachyum is seeking a Physical Design Engineer in Sunnyvale, CA to drive PD for ultra‑high performance chips. You will collaborate with RTL teams, perform floor‑planning, routing, and timing closure, and contribute to clock and power integrity strategies.
The role requires strong Verilog know‑how, ASIC flow experience, and a track record mentoring engineers. Expect a dynamic, cutting-edge environment with competitive compensation and equity.
We would love to welcome a new Senior Physical Design Engineer – High-Performance ASICs to our organisation in Sunnyvale, CA, United States.
The position is based in Sunnyvale, CA, United States.
This opportunity is part of our work in Engineering.
The advertised compensation is 150..
We aim to respond to suitable candidates as soon as possible.
Full responsibilities and requirements are described in the listing above.
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