DFT Engineer

Pay Rate: around/ within $ 65/ Hr. C2C / $60/hr W2

Duration: long-term

Exp. Level: 5 to 15 Yrs,

As a DFT Engineer at QFocus Technologies, you will be responsible for defining, architecting, and executing robust Design-for-Test strategies for high-performance SoCs/ASICs. You will work closely with front-end design, physical design, verification, and product engineering teams to ensure high test coverage, optimal silicon quality, and streamlined post-silicon manufacturing test enablement.

Define and implement comprehensive DFT architectures including Scan, ATPG, MBIST,and JTAG / IEEE standards (1149.1, 1500, 1687 IJTAG).

Perform Scan Chain Insertion, stitching, and optimization to ensure timing closure and power grid compatibility.

Integrate Memory BIST (MBIST) controllers, repair mechanics, and custom memorytest routines.

Generate high-coverage Automatic Test Pattern Generation (ATPG) patterns, including

Stuck-at, At-Speed (Transition/Path Delay), and Cell-Aware testing.

Execute Verilog/System Verilog simulations for gate-level DFT validation, ensuring timingand vector cleanliness (SDF simulation).

Run DFT linting and rule checking using industry-standard tools (e.g., Spy Glass DFT,Tessent, Modus, or TetraMAX)

Translate pre-silicon ATPG and MBIST patterns into tester formats (e.g., WGL, STIL) forATE (Automatic Test Equipment) deployment.

Support post-silicon bring-up in the lab, debugging first-silicon DFT features, patternconversion, and silicon failures.

Collaborate with Product and Test Engineering (PTE) teams to optimize test time,diagnose failure modes, and boost manufacturing yield.

Experience: 3+ years of hands-on DFT experience in advanced SoC/ASIC developmentnodes.

Core Skills & Technical Expertise:
Verilog / System Verilog: Strong proficiency in Hardware Description Languages for DFT integration, wrapper creation, and simulation debugging.

Scan Insertion: Hands-on experience with scan synthesis, compressed scanarchitectures (EDT/Smart Test), and boundary scan integration.

ATPG: Deep experience generating, debugging, and fault-grading Stuck-at, At-speed, and fault-model test patterns.

MBIST: Proven experience with memory BIST insertion, MBIST architecture, and memory repair schemes.

JTAG: Solid understanding of IEEE 1149.1 standards, TAP controllers, and board/chip-level test logic integration.

Post-Silicon Support: Direct experience bringing up patterns on target silicon and supporting production yield ramp.

Familiarity with scripting languages (Tcl, Python, or Perl) for automation of DFT flows.

Knowledge of advanced DFT concepts like High-Speed IO testing, Ser Des loopback, or Analog DFT.

Understanding of synthesis tools (Synopsys Design Compiler, Cadence Genus) and static timing analysis (STA) constraint creation for DFT modes

Best regards,

Office:  Ext: 1001

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