ASIC Implementation Engineer: Timing & Power Optimized

Meta’s Silicon Engineering organization seeks a Staff ASIC Implementation Engineer to lead the physical implementation and synthesis of complex custom ASICs for high-performance AI and computing platforms. The role focuses on end-to-end flows, timing closure, and methodology development.

You will collaborate with RTL, architecture, and physical design teams to optimize area, power, and timing while mentoring engineers and driving sign-off readiness for tape-out.

Consider building your career as a Staff ASIC Implementation Engineer:
Timing & Power Optimized at Anysilicon.

The position is based in Sunnyvale, CA, United States.

This opportunity is part of our work in Engineering, Consulting.

The advertised compensation is 180..

We aim to respond to suitable candidates as soon as possible.

Full responsibilities and requirements are described in the listing above.

Learn more about the Staff ASIC Implementation Engineer:
Timing & Power Optimized role in the description above.