Physical Design Engineer; PnR; ASIC Signoff Expert
Listed on 2026-11-04
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Engineering
Electronics Engineer, Hardware Engineer
Avicena is seeking a Physical Design Engineer (PnR) in Sunnyvale, CA to implement and close digital blocks and top-level partitions of a mixed-signal ASIC. You will work with the PnR lead to take designs from netlist to clean signoff.
Ideal candidates have hands-on experience with Cadence Innovus or Synopsys ICC2/Fusion Compiler, and STA tools such as Tempus or Prime Time, plus physical verification with Calibre or Pegasus on FinFET flows.
We would love to welcome a new Physical Design Engineer (PnR) - ASIC Signoff Expert to our group in Sunnyvale, CA, United States.
Full responsibilities and requirements are described in the listing above.
Learn more about the Physical Design Engineer (PnR) - ASIC Signoff Expert role in the description above.
We appreciate your interest in this position.
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