Senior Timing & Clocking Characterization Engineer; Hybrid
Listed on 2026-11-04
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Engineering
Electronics Engineer, Systems Engineer, Electrical Engineering
The AES Group is seeking a Senior Timing and Clocking Characterization Engineer in Mountain View, CA. You will bridge analog circuit design and digital timing signoff by characterizing clocking blocks across PVT corners, developing timing models, and validating behavior within block-level and full-chip timing environments.
Ideal candidate brings hands-on SPICE characterization, MMMC/OCV methods, and proficiency in Python/Tcl/Perl for automation.
This role, Senior Timing & Clocking Characterization Engineer (Hybrid) at Cha Teck Incorporated, could be your next move.
We invite applications for the Senior Timing & Clocking Characterization Engineer (Hybrid) position located in Sunnyvale, CA, United States.
The following opportunity is for a Senior Timing & Clocking Characterization Engineer (Hybrid) with Cha Teck Incorporated.
Our group is growing, and we are hiring a Senior Timing & Clocking Characterization Engineer (Hybrid) in Sunnyvale, CA, United States.
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