Senior Low-Power Verification Engineer — Physical Design
Listed on 2026-11-04
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Engineering
Hardware Engineer, Electronics Engineer, Test Engineer
Google in Sunnyvale, CA seeks a senior ASIC verification engineer focused on post-layout low-power signoff and TPU architecture to shape AI/ML hardware acceleration.
You will validate UPF, work with Synopsys VCLP, Innovus and Fusion, and drive multi-Voltage design signoff from synthesis to place and route.
The role offers equity and a 15% target bonus, with opportunities to impact Google's next generation TPU systems.
We are seeking a motivated Senior Low-Power Verification Engineer — Physical Design to join Google in Sunnyvale, CA, United States.
The position is based in Sunnyvale, CA, United States.
This opportunity is part of our work in Engineering.
The advertised compensation is 163..
We aim to respond to suitable candidates as soon as possible.
Full responsibilities and requirements are described in the listing above.
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