Pre-Silicon Digital Verification Engineer

Pre-silicon digital verification engineer for mixed signal integrated circuits.

Join an accomplished team at Apple developing custom integrated circuits for Apple's existing and future product lines. As a member of our mixed signal ASIC team, you will be responsible for verifying complex digital IP's. You will work with the system architects and digital designers, making block level specifications clear and precise. You will use the specifications to build verification plans to exercise the functional, performance, stress cases, and error conditions in your blocks.

You will own the creation of the verification test benches, using formal verification and UVM based simulation. Then you will build the testcases using System Verilog Assertions and constrained random UVM testcases to get complete functional and code coverage for your blocks.

You will participate in code reviews of other blocks in the chips, offering proposals to more efficiently achieve our goal of bug free designs on the first tapeout. In addition to traditional digital circuit simulation, you will have the opportunity to learn and use other verification techniques such as formal verification, digital mixed signal verification, and analog mixed signal simulation using state-of-the-art tools.

Although the team is small, we supply silicon to most of Apple's industry leading hardware development teams. We have a close-knit, high performing team ready to ready to mentor engineers entering the mixed signal ASIC development field. Join us in building Apple's next generation products. Do you want to be a part of building the "surprise and delight" in Apple's future products?

• Collaborate in developing precise design specifications for digital control blocks
• Use design specifications to create block and chip level verification plans.
• Architect and create block level verification elements
• Assist in architecting chip and system level verification environments.
• Use System Verilog and UVM to develop drivers, tests, reference models and checkers
• Debug test failures and work with designers to develop fixes
• Use functional and code coverage to track progress and gauge tapeout readiness.

BS and a minimum of 3 years of relevant industry experience

• Extensive course work in digital design and computer architecture
• Foundation in object oriented programming techniques
• Lab courses or work experience with System Verilog
• Familiar with constrained random verification techniques
• Familiarity with clock domain crossing design and verification techniques
• Some course work in analog circuit design