Physical Design Engineer – DIC

We are looking for an experienced Physical Design Engineer – 3

DICto join the team.

Full-Stack Physical Design:
Owning the RTL-to-GDSII flow, including physical-aware synthesis, floor planning, placement, routing, and clock tree synthesis (CTS).

3D-IC and Signoff Execution:
Working on 3D heterogeneous integration and multi-die assemblies, managing TSV (Through-Silicon Via) planning, IR drop, electro-migration (EM), and static timing analysis (STA).

Power & Performance:
Focusing on low-power implementation using UPF/CPF and strict timing closure for high-frequency designs (>1GHz).

Methodology Development:
Collaborating with IP/foundry partners and developing automation scripts in Tcl, Python, or Perl.

Experience: 5+ to 10+ years of hands-on ASIC/SoC Physical Design experience with multiple full-cycle tape-outs at advanced nodes (5nm, 3nm, or 2nm).

Domain Expertise:
Solid understanding of multi-corner multi-mode (MMCM), signal integrity, and 3D packaging technologies.

Tool Proficiency:
Deep experience with industry-standard EDA tools like Cadence (Innovus, Tempus, Voltus) or Synopsys (ICC2, Prime Time).

Scripting

Skills:

Proficiency in Tcl (mandatory), Python, or Perl