Senior Clocking Engineer - Analog Mixed-Signal PLLs
Listed on 2026-11-04
-
Engineering
Electronics Engineer, Systems Engineer
Avicena in Sunnyvale, CA is seeking a Senior/Principal Analog Mixed-Signal Design Engineer, Clocking to own clock generation and distribution across multiple high-speed lanes.
You will drive PLL/DLL integration, jitter budgets, phase alignment, and collaboration with system architects, layout, and verification through silicon bring-up. Prior leadership and strong analytical skills are essential.
We would love to welcome a new Senior Clocking Engineer
- Analog Mixed-Signal PLLs to our organisation in Sunnyvale, CA, United States.
This opportunity is part of our work in Engineering.
The advertised compensation is 180..
We aim to respond to suitable candidates as soon as possible.
Full responsibilities and requirements are described in the listing above.
Learn more about the Senior Clocking Engineer
- Analog Mixed-Signal PLLs role in the description above.
We appreciate your interest in this position.
(If this job is in fact in your jurisdiction, then you may be using a Proxy or VPN to access this site, and to progress further, you should change your connectivity to another mobile device or PC).