Senior ASIC Design & Verification Eng - Hybrid
Listed on 2026-11-04
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Engineering
Test Engineer, Hardware Engineer, Electronics Engineer
Salt in Sunnyvale, CA, is seeking an ASIC Design and/or Verification Engineer (Sr. to Principal) to design, verify and optimize high-performance networking chips in a hybrid work model.
You will write Verilog/System Verilog, develop specs, mentor juniors, and collaborate with Physical Design to meet timing and power targets.
Candidates have 4–15+ years of relevant experience and a strong background in architecture, verification, and scripting with Perl or Python.
Our team is growing, and we are hiring a Senior ASIC Design & Verification Eng
- Hybrid Sunnyvale in San Francisco, CA, United States.
The Senior ASIC Design & Verification Eng
- Hybrid Sunnyvale role at Salt is now open for applications in San Francisco, CA, United States.
Join us at Salt as our next Senior ASIC Design & Verification Eng
- Hybrid Sunnyvale in San Francisco, CA, United States.
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