Senior Physical Design Engineer: Tapeouts & Equity

A semiconductor startup based in California is seeking a Staff/Senior Staff Physical Design Engineer to drive full-chip implementations and meet PPA targets. This role requires 8–12 years of experience in ASIC physical design, specializing in tools like Synopsys ICC2 and Cadence Innovus. The ideal candidate will have a strong background in full-chip or large block implementations and a hands-on approach to debugging.

The compensation range is competitive, between $200,000 and $220,000 per year.
Join us at Bolt Graphics, Inc. as our next Senior Physical Design Engineer:
Tapeouts & Equity in Sunnyvale, CA, United States. All applications are reviewed carefully by our team. The position is based in Sunnyvale, CA, United States. This opportunity is part of our work in Engineering. The advertised compensation is 200.. We aim to respond to suitable candidates as soon as possible.