Senior SI/PI Engineer .5D/3D Chip- Systems
Listed on 2026-11-04
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Engineering
Systems Engineer, Test Engineer, Electronics Engineer, Hardware Engineer
Meta is seeking a seasoned Signal Integrity and Power Integrity engineer to own chip-package-system co-design for AI accelerators and HPC silicon. You will drive SI/PI requirements from architecture through post-silicon validation across 2.5D/3D packaging, coordinating with ASIC, package, PCB, and foundry partners to ensure reliable high-speed interfaces and power delivery.
The role involves leading pre/post-layout simulations, modeling, and methodology development to meet strict performance and
We are seeking a motivated Senior SI/PI Engineer for 2.5D/3D Chip-Package Systems to join Meta in Sunnyvale, CA, United States.
Join Meta and contribute to our ongoing work.
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This posting is for the Senior SI/PI Engineer for 2.5D/3D Chip-Package Systems role at Meta, based in Sunnyvale, CA, United States.
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