DFT Lead - Mixed-Signal ASIC Test Architect
Listed on 2026-11-04
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Engineering
Test Engineer, Electronics Engineer, Hardware Engineer
Avicena in Sunnyvale, CA is seeking a DFT Lead to own the test architecture of our mixed-signal ASIC, from scan and BIST through analog test access and production test delivery. You will define the strategy, implement and verify it, and work with product/test engineering to bring it up on the tester.
You will lead DFT engineers, drive coverage targets, collaborate with design on loopback modes, PRBS, memory BIST, and IEEE 1149.1/1687 access, and diagnose silicon issues to reduce test time and
We are currently recruiting a DFT Lead - Mixed-Signal ASIC Test Architect for our team in Sunnyvale, CA, United States.
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